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1 high performance 1a linear regulator with programmable current limiting ISL80101a the ISL80101a is a low dropout voltage, single output ldo with programmable current limi ting. this ldo operates from input voltages of 2.2v to 6v, and is capable of providing output voltages of 0.8v to 5v. other custom voltage options are available upon request. a sub-micron bicmos process is utilized for this product family to deliver the best in class analog performance and overall value. the programmable current limiting improves system reliability of end applications. an external capacitor on the soft-start pin provides an adjustable soft-starting ramp. the enable feature allows the part to be placed into a low quiescent current shutdown mode. this cmos ldo will consume significantly lower quiescent current as a function of load compared to bipolar ldos, which translates into higher efficien cy and packages with smaller footprints. quiescent current is modestly compromised to achieve a very fast load transient response. table 1 shows the differences between the ISL80101a and others in its family: features ? 2% v adj accuracy guaranteed over line, load and t j = -40c to +125c ? very low 212mv dropout voltage at v in = 4.5v ? high accuracy current limit programmable up to 1.75a ? very fast transient response ? 100v rms output noise ? power-good output ?programmable soft-start ? over-temperature protection ?small 10 ld dfn package applications ? telecommunications and networking ?medical equipment ? instrumentation systems ?usb devices ?gaming ?routers and switchers table 1. key differences between family of parts part number i limit (default) programmable i set ISL80101 1.75a no ISL80101a 1.62a yes isl80121-5 0.75a yes v in pg enable ss gnd v in 1 2 5 4 7 10 9 6 10k 100k 10f 5.0v 5% 3.3v adj 2.61k 0.464k ISL80101a c ss c pb c out r 1 0.01f r 3 r 2 100pf 3 8 i set r set 10f c in i limit 1.62 2.9x 2xv in 1 ? () r set k () -------------------------------------------------------- ? = v out v out figure 1. typical application r set (k ) current limit (a) v in = 5.0v v in = 5.5v v in = 4.5v 10 100 1000 1.5 1.2 0.9 0.6 0.3 0.0 february 24, 2011 fn7712.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL80101a 2 fn7712.2 february 24, 2011 block diagram ordering information thermal shutdown current limiter voltage reference power good ss enable gnd pg adj adjustable voltage version sense fixed voltage version i set v out v in part number (notes 1, 2) part marking v out voltage (note 3) temp. range (c) package (pb-free) pkg dwg. # ISL80101airajz dzac adj -40 to +125 10 ld 3x3 dfn l10.3x3 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. the 1.5v, 3.3v and 5v fixed output voltages will be released in the future. please contact intersil marketing for more detail s.
ISL80101a 3 fn7712.2 february 24, 2011 pin configurations ISL80101a (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 v out v out adj pg gnd v in v in i set enable ss pad pin descriptions pin number pin name description 1, 2 v out output voltage. a minimum 10uf x5r/x7r output capacitor is required for stability. see ?external capacitor requirements? on page 8 for more details. 3 adj ldo output feedback input. to adjust the output voltag e, connect this pin to a resistive voltage divider from the v out to gnd. 4pgv out in regulation signal. logic low indicates v out is not in regulation, and mu st be grounded if not used. 5gndground. 6 ss external capacitor adjusts in-rush current. 7enable v in -independent chip enable. ttl and cmos compatible. 8i set current limit setting. current limit is 1. 62a when this pin is left floating. this default value can be increased by tying r set to gnd, or decreased by tying r set to v in . see ?programmable current limit? on page 7 for more details. 9, 10 v in input supply. a minimum of 10f x5r/x7r input capacitor is required for stability. see ?external capacitor requirements? on page 8 for more details. - epad epad at ground potential. soldering it directly to gn d plane is required for thermal considerations. see ?power dissipation and thermals? on page 9 for more details.
ISL80101a 4 fn7712.2 february 24, 2011 absolute maximum ratings (note 6) thermal information v in relative to gnd.................................................................... -0.3v to +6.5v v out relative to gnd ................................................................ -0.3v to +6.5v pg, enable, sense, ss, i set relative to gnd ...................................................................... -0.3v to +6.5v esd rating human body model (tested per jedec)............................................. 2.5kv machine model (tested per jedec) ..................................................... 250v latch up (tested per jedec)..........................................100ma @ +85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld 3x3 dfn package (notes 4, 5). . . . . 48 7 maximum junction temperature (plastic package).........................+150c storage temperature range ............................................... -65c to +150c pb-free reflow profile................................................................see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions (note 7) junction temperature range (t j ) ...................................... -40c to +125c v in relative to gnd ...........................................................................2.2v to 6v v out range....................................................................................800mv to 5v pg, enable, sense, ss, i set relative to gnd................................. 0v to 6v pg sink current......................................................................................... 10ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6v of 1% 7. electromigration specification defined as lifetime average junc tion temperature of +110c where max rated dc current = lifeti me average current. electrical specifications unless otherwise noted, all parameters are estab lished over the followin g specified conditions: v in =v out + 0.4v, v out = 3.3v, c in = c out = 10 f, t j = +25 c, i load = 0a applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?functional description? on page 7 and tech brief tb379 . boldface limits apply over the operating temperature range, -40c to +125c. pulse load techniques used by ate to ensure t j = t a defines established limits. parameter symbol test conditions min (note 8) typ max (note 8) units dc characteristics dc adj pin voltage accuracy v adj v out + 0.4v < v in < 6v; 0a < i load < 1a 490 500 510 mv dc input line regulation v out / v in v out + 0.4v < v in < 6.0v, v out = 5.0v 0.2 1 % dc output load regulation v out 0a < i load < 1a -1 % feedback input current v adj = 0.5v 0.01 1 a ground pin current i q i load = 0a, 2.2v < v in <6v 3 5 ma i load = 1a, 2.2v < v in <6v 5 7 ma ground pin current in shutdown i shdn enable = 0.2v, v in = 6v 0.2 12 a dropout voltage (note 9) v do i load = 1a, v in = 4.5v, v sense = 0v 90 212 mv output current limit i limit v out = 2v, 4.5v < v in < 5.5v, i set is floating 1.62 a v out = 2v, v in = 5.0v, r set = 25.5k 0.540 0.640 0.740 a thermal shutdown temperature tsd v out + 0.4v < v in < 6v 160 c thermal shutdown hysteresis (rising threshold) tsdn v out + 0.4v < v in < 6v 30 c ac characteristics input supply ripple rejection psrr f = 1khz, i load = 1a; v in = 5.0v 48 db f = 120hz, i load = 1a; v in = 5.0v 48 db output noise voltage i load = 10ma, bw = 300hz < f < 300khz 100 v rms enable pin characteristics turn-on threshold v en(high) 2.2v < v in < 6v 0.3 0.8 1.0 v
ISL80101a 5 fn7712.2 february 24, 2011 hysteresis (rising threshold) v en(hys) 2.2v < v in < 6v 10 80 200 mv enable pin turn-on delay t en c out = 10f, i load = 1a 80 s enable pin leakage current v in = 6v, enable = 3v 1 a soft start characteristics reset pull-down current i pd v in = 5.4v, enable = 0v, ss = 1v 0.5 1 1.3 ma soft start charge current i chg -3.3 -2 -0.8 a pg pin characteristics v out pg flag threshold 75 84 92 %v out v out pg flag hysteresis 4% pg flag low voltage i sink = 500a 47 100 mv pg flag leakage current v in = 6v, pg = 6v 0.05 1 a notes: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 9. dropout is defined by the difference in supply v in and v out when the output is below its nominal regulation. electrical specifications unless otherwise noted, all parameters are estab lished over the followin g specified conditions: v in =v out + 0.4v, v out = 3.3v, c in = c out = 10 f, t j = +25 c, i load = 0a applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?functional description? on page 7 and tech brief tb379 . boldface limits apply over the operating temperature range, -40c to +125c. pulse load techniques used by ate to ensure t j = t a defines established limits. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
ISL80101a 6 fn7712.2 february 24, 2011 typical operating performance unless otherwise noted: v in = 5v, v out = 3.3v, c in = c out = 10f, t j = +25c, i l = 0a. figure 2. dropout vs load figure 3. v adj vs temperature figure 4. output voltage vs supply voltage f igure 5. output voltage vs output current figure 6. ground current vs load current f igure 7. ground curren t vs supply voltage 0 30 60 90 120 150 0 0.2 0.4 0.6 0.8 1.0 load current (a) dropout (mv) -40c +25c +125c 0.495 0.496 0.497 0.498 0.499 0.500 0.501 0.502 0.503 0.504 0.505 -40 -20 0 20 40 60 80 100 120 temperature (c) v adj (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0246 supply voltage (v) output voltage (v) 135 +125c +25c -40c -1.8 -1.2 -0.6 0 0.6 1.2 1.8 0 0.25 0.50 0.75 1.00 output current (a) v out (%) +125c +25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.2 0.4 0.6 0.8 1.0 load current (a) ground current (ma) -40c +25c +125c 0 1 2 3 4 5 24 input voltage (v) ground current (ma) 356
ISL80101a 7 fn7712.2 february 24, 2011 functional description input voltage requirements ISL80101a is capable of delivering output voltages from 0.8v to 5.0v. due to the nature of an ldo, v in must be some margin higher than v out plus dropout at the maximum rated current of the application if active filtering (psrr) is expected from v in to v out . the generous dropout specification of this family of ldos allows applications to design fo r a level of efficiency that can accommodate profiles sma ller than the to220/263. programmable current limit the ISL80101a protects against overcurrent due to short-circuit and overload conditions applie d to the output. when this happens, the ldo performs as a constant current source. if the short-circuit or overload condition is removed, the output returns to normal voltage regulation operation. the current limit is set at 1.62a by default when the i set pin is left floating. this limit can be increased by tying a resistor r set from the i set pin to ground. the current limit is determined by r set as shown in equation 1. do not short this pin to ground. increasing the current limit past 1.75a may cause damage to the part and is highly discouraged. the current limit can be decreased from the 1.62a default by tying r set from the i set pin to v in . the current limit is then determined by both r set and v in following equation 2. figure 12 shows the relationship between r set and the current limit when r set is tied from the i set pin to v in for various v in values. figure 8. enable start-up figure 9. current limit vs temperature figure 10. load transient response figure 11. psrr vs frequency typical operating performance unless otherwise noted: v in = 5v, v out = 3.3v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) enable (5v/div) ss (1v/div) v out (2v/div) pg (2v/div) time (5ms/div) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -40 10 60 110 temperature (c) current limit (a) r set = 25.5k ? r set = open v out at 50mv/div i out = 1a i out = 10ma time (20s/div) 0 10 20 30 40 50 60 70 80 90 100 1k 10k 100k 1m frequency (hz) psrr (db) 0ma 500ma 1000ma 100ma (eq. 1) i limit 1.62 2.9 r set k () -------------------------- + = (eq. 2) i limit 1.62 2.9 2 v in 1 ? () r set k () ----------------------------------------------- ? =
ISL80101a 8 fn7712.2 february 24, 2011 . enable operation the enable turn-on threshold is typically 800mv with 80mv of hysteresis. an internal pull-up or pull-down resistor to change these values is available upon request. as a result, this pin must not be left floating, and should be tied to v in if not used. a 1k to 10k pull-up resistor is required for applications that use open collector or open drain outputs to control the enable pin. the enable pin may be connected directly to v in for applications with outputs that are always on. power-good operation pg is a logic output that indicates the status of v out , current limit tripping, and v in . the pg flag is an open-drain nmos that can sink up to 10ma during a fault condition. the pg pin requires an external pull-up resistor typically connected to the v out pin. the pg pin should not be pulled up to a voltage source greater than v in . pg goes low when the output voltage drops below 84% of the nominal output voltage, the current lim it faults, or the input voltage is too low. pg functions during shutdown, but not during thermal shutdown. for applications not using this feature, connect this pin to ground. soft-start operation the soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or ldo enable. this start-up ramp time can be set by adding an external capacitor from the ss pin to ground. an internal 2a current source charges up this c ss and the feedback reference voltage is clamped to the voltage across it. the start-up time is set by equation 3. equation 4 determines the c ss required for a specific start-up in-rush current, where v out is the output voltage, c out is the total capacitance on the output and i inrush is the desired in-rush current. the external capacitor is always discharged to ground at the beginning of start-up or enabling. output voltage selection an external resistor divider is used to scale the output voltage relative to the internal reference voltage. this voltage is then fed back to the error amplifier. the output voltage can be programmed to any level between 0.8v and 5v. an external resistor divider, r 2 and r 3 , is used to set the output voltage as shown in equations 5 and 6. pl ease see table 2 on page 9 for recommended values of r 2 and r 3 . external capacitor requirements external capacitors are required for proper operation. careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. output capacitor the ISL80101a applies state-of-the-art internal compensation to keep the selection of the output capacitor simple for the customer. stable operation over full temperature, v in range, v out range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 10f x5r/x7r is used for local bypass on v out . this output capacitor must be connected to the v out and gnd pins of the ldo with pcb traces no longer than 0.5cm. there is a growing trend to use very-low esr multilayer ceramic capacitors (mlcc) because they can support fast load transients and also bypass very high frequency noise from other sources. however, the effective capacitance of mlccs drops with applied voltage, age, and temperature. x7r and x5r dielectric ceramic capacitors are strongly recommended as they ty pically maintain a capacitance range within 20% of nominal voltag e over full operating ratings of temperature and voltage. additional capacitors of any value in ceramic, poscap, alum/tantalum electrolytic types may be placed in parallel to improve psrr at higher frequenc ies and/or load transient ac output voltage tolerances. phase boost capacitor a small phase boost capacitor, c pb , can be placed across the top resistor, r 3 , in the feedback resistor divider network in order to place a zero at: this zero increases the crossover frequency of the ldo and provides additional phase result ing in faster load transient response. it is also important to note that the ldo stability and load transient are affected by the type of output capacitor used. for optimal result, empirical tuning is suggested for each specific application. figure 12. current limit vs rset at different v in r set (k ) current limit (a) v in = 5.0v v in = 5.5v v in = 4.5v 10 100 1000 1.5 1.2 0.9 0.6 0.3 0.0 t start c ss x0.5 () 2 a -------------------------- - = (eq. 3) c ss v out xc out x2 a ) () i inrush x0.5v ---------------------------------------------------- - = (eq. 4) v out 0.5v r 3 r 2 ------ - 1 + ?? ?? ?? = (eq. 5) r 3 r 2 v out 0.5v ------------ - 1 ? ?? ?? = (eq. 6) f z 1 2 xr 3 xc pb ------------------------------- - = (eq. 7)
ISL80101a 9 fn7712.2 february 24, 2011 table 2 shows the recommended c pb , r 3 and r 2 for different output voltage and ceramic c out . input capacitor for proper operation, a minimu m capacitance of 10f x5r/x7r is required at the input. this ceramic input capacitor must be connected to the v in and gnd pins of the ldo with pcb traces no longer than 0.5cm. power dissipation and thermals the junction temperature must not exceed the range specified in the ?recommended operating conditions (note 7)? on page 4. the power dissipation can be calculated by using equation 8: the maximum allowable ju nction temperature, t j(max) and the maximum expected ambi ent temperature, t a(max) determine the maximum allowable power dissipation, as shown in equation 9: ja is the junction-to-ambient thermal resistance. for safe operation, ensure that the power dissipation p d , calculated from equation 8, is less than the maximum allowable power dissipation p d(max) . the dfn package uses the copper ar ea on the pcb as a heat-sink. the epad of this package must be soldered to the copper plane (gnd plane). figure 13 shows a curve for the ja of the dfn package for different copper area sizes. thermal fault protection the power level and the thermal impedance of the package (+48c/w for dfn) determine wh en the junction temperature exceeds the thermal shutdown temper ature. in the event that the die temperature exceeds around +160c, the output of the ldo will shut down until the die temperat ure cools down to about +130c. general powerpad design considerations figure 14 shows the recommended us e of vias on the thermal pad to remove heat from the ic. this typical array populates the thermal pad footprint with vias spaced thr ee times the radius distance from the center of each via. small via size is advisable, but not to the extent that solder reflow becomes difficult. all vias should be connected to the pad potential, with low thermal resistance for efficient heat tran sfer. complete connection of the plated-through hole to each pl ane is important. it is not recommended to use ?thermal relief ? patterns to connect the vias. table 2. recommended c pb for different v out and c out v out (v) r 3 (k ) r 2 (k ) c out ( f) c pb (pf) 5.0 2.61 0.287 10 100 3.3 2.61 0.464 10 100 2.5 2.61 0.649 10 82 1.8 2.61 1.0 10 82 1.5 2.61 1.3 10 68 1.5 2.61 1.3 22 150 1.2 2.61 1.87 22 120 1.2 2.61 1.87 47 270 1.0 2.61 2.61 47 220 0.8 2.61 4.32 47 220 p d v in v out ? () i out v in i gnd + = (eq. 8) p dmax () t jmax () t a ? () ja ? = (eq. 9) figure 13. 3mmx3mm-10 pin dfn on 4-layer pcb with thermal vias ja vs epad-mount copper land area on pcb 46 44 42 40 38 36 34 24681012141618202224 epad-mount copper land area on pcb, mm 2 ja , c/w figure 14. pcb via pattern
ISL80101a 10 fn7712.2 february 24, 2011 revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 2/2/11 fn7712.2 1. on page 1, ?features? a."1.8% vout accuracy guaranteed?" chan ged to "2% vadj accuracy guaranteed?" 2. figure 1 on page 1 a."typical applications" changed to "typical application" b."82pf" for cpb changed to "100pf" 3. on page 3, pin number 8 a. on "description" of iset, change 2nd sentence from "current limit is 0.75ma when?" to "current limit is 1.62a when?" 4. on page 4, ?electrical specifications? a."dc input line regulation" given own line, added symbol, and changed test conditions b. ?feedback input current?, added typical "0.01" and max "1" with units "a" 5. on page 5, ?electrical specifications? a. ?pg pin characteristics? ?vout pg flag threshold?, typical "85" changed to "84" %vout 7. on page 7, ?programmable current limit? a. equation 1 changed to "ilimit=1.62+?" b. equation 2 changed to "ilimit=1.62-?" 8. added "the current limit can be decreased from the 0.75a default?" changed to "the current limit can be decreased from the 1.62a default?" on page 7, between equation 1 and equation 2 9. on page 7, beginning of last paragraph a. "figure 11 shows the relationship?" chan ged to "figure 12 shows the relationship?" 10. ?external capacitor requirements? on page 8: a. "the isl80121-5 applies?" changed to "the ISL80101a applies? 11. on page 4, ?electrical specifications?, ?dc characteristics?, ?output current limit? a. "vout = 2v, vin = 5.5v, rset = 25.5k " change d to ""vout = 2v, vin = 5.0v, rset = 25.5k " 12. on page 4, ?electrical specifications?, ?ac characteristics?, ?input supply ripple rejection? a. "58db" typical changed to "48" b. "62db" typical changed to "48" 13. on page 8, revised figure 12. updated same graphic on page 1 14. throughout: all "vin" changed to "v in " 15. throughout: all "vout" changed to "v out " 16. throughout: all "rset" changed to "r set " 17. throughout: all "iset" changed to "i set " 18. throughout: all "en" and "enable" changed to "enable" 19. throughout: all "pgood" changed to "pg" 20. ?block diagram? on page 2, subscripted pin names for v in , v out , i set . changed pgood to pg 21. on page 3, epad description a. "directly to gnd plane is opti onal." changed to "directly to gnd plane is required for thermal considerations. see ?power dissipation an d thermals? on page 9 for more details." 22. on page 1, in paragraph 2, "the programmable current limiting improves system reliability of applications" changed to "the programmable current limiting improves system reliability of end applications." 23. on page 1, ?features?, "programmable soft-starting" changed to "programmable soft-start" 24. on page 4, ?electrical specifications?, ?dc charac teristics?, "dc output voltage accuracy" changed to ?dc adj pin voltage accuracy? 25. on page 5, notes 10 and 11 deleted (they were not referenced in the spec table). 26. ?output voltage selection? on page 8, "an external re sistor divider, r2 and r3, is used to set the output voltage as shown in equation 5. the recommended value for r3 is 500 ? to 1k ? . r2 is then chosen according to equation 6." changed to "an external resistor divider, r2 and r3, is used to set the output voltage as shown in equations 5 and 6. please see table 2 on page 9 for recommended values of r2 and r3." 29. added ?general powerpad design considerations? on page 9 30. revised figure 8 12/6/10 fn7712.1 modified ?block diagram? on page 2. in ?ground pin current? on page 4 test conditions: -changed 1st line from "v out + 0.4v < v in < 5v, vsense = 0v" to "i load = 0a, 2.2v < v in <6v" -changed 2nd line from "v out + 0.4v < v in < 6v, vsense = 0v" to "i load = 1a, 2.2v < v in <6v" figure 2 ?dropout vs load? on page 6: -switched colors on 25c and 125c. 11/29/10 fn7712.0 initial release
ISL80101a 11 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7712.2 february 24, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
ISL80101a 12 fn7712.2 february 24, 2011 package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 6, 09/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. lead width applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 1 package 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 outline max (4x) 0.10 ab 4 c m 0.415 0.23 0.35 0.200 2 4

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